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Results: 1614

#	Item
311	R ET C ON: Transactional Repair without Replay Colin Blundell Arun Raghavan Milo M. K. Martin Add to Reading List Source URL: www.cis.upenn.edu Language: English - Date: 2010-04-10 11:24:17 Data Transaction processing Abstract interpretation Symbolic execution MIX Hash table ATS CPU cache Extensible Storage Engine Computing Computer memory Computer programming
312	Microsoft PowerPoint - CPU Caches.pptx Add to Reading List Source URL: www.aristeia.com Language: English - Date: 2015-01-10 11:21:48 Computing Computer architecture CPU cache Cache Translation lookaside buffer Memory hierarchy Computer memory Computer hardware Central processing unit
313	Computer Science 252: Graduate Computer Architecture University of California Dept. of Electrical Engineering and Computer Sciences David E. Culler TA: Steve Sorkin Take Home due 5/20 Spring 2003 Add to Reading List Source URL: www.cs.berkeley.edu Language: English - Date: 2003-06-11 14:32:04 Central processing unit CPU cache Cache Computer memory Parallel computing Processor register Register renaming Cell Computer architecture Computing Computer hardware
314	Leveraging Value Locality in Optimizing NAND Flash-based SSDs Aayush Gupta, Raghav Pisolkar, Bhuvan Urgaonkar, and Anand Sivasubramaniam {axg354,rvp116,bhuvan,anand}@cse.psu.edu Department of Computer Science and Enginee Add to Reading List Source URL: static.usenix.org Language: English - Date: 2010-12-17 12:27:20 Solid-state drive Flash memory Wear leveling CPU cache Cache Garbage collection OCZ Technology Paging Flash file system Computer hardware Computer memory Computing
315	MECHANISMS FOR UNBOUNDED, CONFLICT-ROBUST HARDWARE TRANSACTIONAL MEMORY Colin Blundell A DISSERTATION in Computer and Information Science Add to Reading List Source URL: www.cis.upenn.edu Language: English - Date: 2010-09-28 10:25:27 Computing Computer memory Data Transactional memory Software transactional memory Linearizability CPU cache Parallel computing Cache Transaction processing Concurrency control Data management
316	CCCG 2007, Ottawa, Ontario, August 20–22, 2007 Cache-Oblivious Output-Sensitive Two-Dimensional Convex Hull Peyman Afshani∗ Abstract Add to Reading List Source URL: cccg.ca Language: English - Date: 2008-10-28 21:25:58 Cache Mathematical analysis Theoretical computer science Cache-oblivious algorithm Kirkpatrick–Seidel algorithm CPU cache Convex hull Algorithm Big O notation Convex hull algorithms Analysis of algorithms Mathematics
317	A Trace-Driven Analysis of Name and Attribute Caching in a Distributed System Ken W. Shirriff John K. Ousterhout Computer Science Division Electrical Engineering and Computer Sciences Add to Reading List Source URL: www.stanford.edu Language: English - Date: 2009-09-07 02:00:53 Memory management Central processing unit Computer memory CPU cache Lookup table Sprite Cache algorithms Database caching Computing Cache Computer hardware
318	The University of Hertfordshire The Challenges facing Libraries and Imperative Languages from Massively Parallel Architectures Jason McGuiness Add to Reading List Source URL: www.accu.org Language: English - Date: 2008-04-14 03:49:41 Central processing unit Parallel computing Classes of computers Microprocessors Instruction-level parallelism Superscalar Very long instruction word CPU cache Instruction set Computer architecture Computing Computer hardware
319	CACHE REPLACEMENT WITH MEMORY ALLOCATION Shahram Ghandeharizadeh Sandy Irani Jenny Lam Add to Reading List Source URL: www.ics.uci.edu Language: English - Date: 2015-01-02 20:44:15 Paging Priority queue CPU cache Page replacement algorithm Computer memory Virtual memory Cache
320	5 Steps of MIPS Datapath Instruction Fetch Next PC Next SEQ PC Add to Reading List Source URL: www.cs.berkeley.edu Language: English - Date: 2003-06-11 14:31:47 Cache Computing Computer architecture Virtual memory Classic RISC pipeline CPU cache Translation lookaside buffer Motorola 68000 family Computer hardware Central processing unit Computer memory

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